1. Field of the Invention
Embodiments relate to a memory chip. More particularly, embodiments relate to a method for shifting the phase of a clock signal and a memory chip using the same.
2. Description of the Related Art
Semiconductor memory devices transmit and receive data in response to a clock signal. That is, semiconductor memory devices sample data in synchronization with a rising edge or a falling edge of a clock signal.
To transmit and receive the data between the transmitter and the receiver, the clock signal must be correctly synchronized with the data. When pulses of the clock signal are not exactly synchronized with edges of the waveform of data bits transmitted and received, the probability that an error is generated in the data bits increases. Accordingly, it is preferable that the pulses of the clock signal are synchronized with middle points of periods in which the data bits are sampled without error. Therefore, semiconductor memory devices perform an operation of detecting middle points of periods in which data bits are sampled without error as an initial operation.
FIG. 1 illustrates data DATA and a clock signal CLK in a conventional clock phase shifting method. Referring to FIG. 1, the conventional method determines whether the data DATA sampled in synchronization with the clock signal CLK has an error while shifting the phase of the clock signal CLK. For the particular example in FIG. 1, data DATA is one bit data, the clock signal CLK has a cycle of 360°, and the phase of the clock signal CLK is shifted by 10°.
An edge of a pulse of the clock signal CLK is synchronized with an edge of the waveform of the data bit DATA. When the clock signal CLK has a phase of 0°, the data bit DATA sampled in synchronization with the clock signal CLK having a phase of 0° has an error (F) if the clock signal CLK is synchronized with the left edge of the waveform of the data bit DATA. Then, the phase of the clock signal CLK is shifted by 10° and the data bit DATA is sampled in synchronization with the clock signal CLK having a phase of 10°. In this case, the sampled data bit DATA also has an error (F). In this manner, the data bit DATA is sampled while the phase of the clock signal CLK is shifted by 10° to determine whether the data bit DATA has an error. In FIG. 1, the data bit DATA has an error (F) when sampled in synchronization with the clock signal CLK having phases of 0°, 10°, 20° and 30° and does not have an error (P) when sampled in synchronization with the clock signal CLK having phases of 40°, 50°, . . . , 340°. Furthermore, the data bit DATA has an error (F) when sampled in synchronization with the clock signal CLK having phases of 350° and 360°.
As described above, the conventional method determines whether each data bit has an error for every phase of a clock signal while the phase of the clock signal is shifted. However, the conventional method requires an excessively long period of time to determine whether data has an error.